The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer damascene interconnects (e.g., vias) and intra-layer interconnects having increasing aspect ratios (opening depth to diameter ratio) of greater than about 4.
In particular, in forming a dual damascene by a via-first method where the via opening is first formed in one or more dielectric insulating layers followed by forming an overlying and encompassing trench opening for forming a metal interconnect line, several processing steps are required which entail exposing the via opening to dry etching chemistries. As a result, the sidewalls of the via are subject to etching which causes variation in the via opening profile leading to undesirable variations in via electrical resistances and capacitances in the completed metal filled damascene.
Approaches to prevent exposing the via opening to etching process have included forming via filling materials within the via opening to protect the via opening from exposure to subsequent processes. For example, prior art processes typically include forming a via filling material within the via opening followed by etch back of the via filling material to form via plug prior to a photolithographic patterning process for forming the trench.
One problem with prior art processes for forming via plugs, are the several processing steps required to form the dual damascene structure. For example, during the etchback process, for example a plasma ashing process, to form the via plug, there is a tendency to form via plug filling particulate contamination remaining over the process wafer surface. Since the surface particulate contamination compromises the reliability of a subsequent trench patterning process, a separate wafer cleaning process is required prior to trench patterning. The separate processing steps of via plug filling layer deposition, etchback to form a via plug, and process wafer cleaning are time consuming.
Other related problems with prior art processes include the fact that exposed nitride layers following the etchback process may undesirably react with the overlying trench photoresist. For example, as feature sizes decrease to sub-quarter-micron dimensions photolithographic patterning processes require activating light (radiation) of increasingly smaller wavelength. For 0.25 micron and below CMOS technology, deep ultraviolet (DUV) positive photoresists have become necessary to achieve the desired resolution. Typically DUV photoresists are activated with activating light source wavelengths of less than about 250 nm, for example, commonly used wavelengths include 193 nm and 248 nm. Many DUV photoresists are chemically amplified using a photoacid generator activated by the light source to make an exposed photoresist area soluble in the development process.
One problem affecting DUV photoresist processes is the potential interference of residual nitrogen-containing species, for example amines, with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use of metal nitride layers such as silicon oxynitride (e.g., SiON), which is commonly used as a bottom-anti-reflectance coating (BARC), also referred to as a dielectric anti-reflectance coating (DARC). Metal nitride layers, such as silicon oxynitride and silicon nitride are also frequently used as etching stop layers. The DARC layers and etching stop layers are typically exposed in the via plug etchback process leading to potential nitrogen containing species contamination of a subsequently deposited trench line DUV photoresist in a trench line patterning process. For example, it is believed that nitrogen containing species neutralize photogenerated acid catalysts which render portions of the photoresist insoluble in the developer. As a result, residual photoresist remains on patterned feature edges, sidewalls, or floors of features, detrimentally affecting subsequent anisotropic etching profiles.
There is therefore a need in the semiconductor processing art to develop an improved dual damascene manufacturing process to improve via protection while avoiding photoresist poisoning effects including a more efficient process to reduce a process cycle time thereby increasing wafer throughput.
It is therefore an object of the invention to provide an improved dual damascene manufacturing process to improve via protection while avoiding photoresist poisoning effects including providing a more efficient process to reduce a process cycle time thereby increasing wafer throughput, in addition to overcoming other shortcomings and deficiencies in the prior art.